B1: Mystery Gate #1
Toggle switches A and B to observe output Y. Identify the logic gate in the mystery box!
Solution & Explanation:
The gate is a NAND gate. Output Y is 1 for (0,0),(0,1),(1,0) and only 0 when both A=1 and B=1 — inverted AND truth table.
B2: Mystery Gate #2
Toggle inputs A and B. This gate produces 1 only when inputs are different. Which gate is it?
Solution & Explanation:
The gate is an XOR (Exclusive OR) gate. Y=1 when A≠B and Y=0 when A=B.
B3: Absorption Law #1
Simplify the Boolean expression: Y = A + A·B
Solution & Explanation:
Y = A. By Absorption Law: A + A·B = A(1 + B) = A(1) = A.
B4: 3-Input AND Truth Table
Toggle A, B, and C. When does output Y become 1?
Solution & Explanation:
When all inputs A, B, C are 1. An n-input AND gate requires ALL inputs to be HIGH for output Y = 1.
B5: NOR Gate Identity
For a NOR gate Y = !(A + B), when is Y equal to 1?
Solution & Explanation:
NOR = OR then NOT. OR is 0 only when both inputs are 0 → NOT(0) = 1. So A=0 and B=0.
I1: De Morgan's Law (NAND Dual)
Which expression equals !(A · B) by De Morgan's First Theorem?
Solution & Explanation:
Ā + B̄. De Morgan's: complement of a product = sum of complements: !(A·B) = !A + !B.
I2: De Morgan's Law #2 (NOR Dual)
Which expression equals !(A + B) by De Morgan's Second Theorem?
Solution & Explanation:
Ā · B̄. De Morgan's Second Theorem: complement of a sum = product of complements.
I3: XOR In terms of NAND Only
How many 2-input NAND gates are needed to build a 2-input XOR gate?
Solution & Explanation:
4 NAND gates. Standard 2-level XOR using NAND: Y = NAND(NAND(A, NAND(A,B)), NAND(B, NAND(A,B))).
I4: Boolean Expression to SOP
Convert Y = (A + B) · (A + C) into simplified Sum-of-Products (SOP) form.
Solution & Explanation:
Y = A + B·C. Expand: A·A + A·C + A·B + B·C = A + A(C+B) + B·C = A(1 + C + B) + B·C = A + B·C.
I5: K-Map Grouping Count
In a 4-variable K-Map, a quad (group of 4 1s) eliminates how many variables from the product term?
Solution & Explanation:
2 variables eliminated. Group of 2^k minterms eliminates k variables. For quad k=2 → 2 variables eliminated.
C1: CMOS Inverter Transistor Count
How many transistors are required to construct a standard static CMOS NOT gate (Inverter)?
Solution & Explanation:
2 Transistors: 1 PMOS in Pull-Up Network (PUN) + 1 NMOS in Pull-Down Network (PDN).
C2: CMOS NOR Gate Transistor Count
In a 2-input CMOS NOR gate, how are the PMOS transistors arranged in the Pull-Up Network (PUN)?
Solution & Explanation:
Series connection. NOR PUN requires Y=1 only when A=0 AND B=0 → both PMOS must conduct in series.
C3: CMOS Pull-Up vs Pull-Down
Which network in static CMOS is responsible for driving the output node Y to VDD (Logic 1)?
Solution & Explanation:
Pull-Up Network (PUN) composed of PMOS transistors drives output HIGH (VDD) because PMOS passes a strong 1.
C4: CMOS 3-Input Majority Function
Test the Majority logic widget. Output Y is HIGH when 2 or more inputs are 1. What is the Boolean expression?
Solution & Explanation:
Y = A·B + B·C + A·C. Checks if any pair is (1,1): AB, BC, or AC.
