B1: AND Gate Identity Law Which correctly simplifies Y = A · 1 using Boolean identity laws?
Y = A Y = 1 Y = 0 Y = Ā
💡 View Solution Solution & Explanation: Y = A . Identity Law: ANDing any variable with 1 returns the variable. A · 1 = A.
B2: OR Gate Complement Law What is the result of Y = A + Ā (A OR NOT-A)?
Y = 1 (always) Y = 0 (always) Y = A Y = Ā
💡 View Solution Solution & Explanation: Y = 1 . Complement Law: A variable OR'd with its complement is always 1 — one of them is always HIGH.
B3: XNOR Equality Detector An XNOR gate outputs 1 when inputs are equal. For A=0, B=0, what is Y?
Y = 1 Y = 0 Undefined Toggles randomly
💡 View Solution Solution & Explanation: Y = 1 . A=B=0 are equal → XNOR=1. (XOR(0,0)=0, then NOT=1.)
I1: Consensus Theorem Simplify Y = A·B + Ā·C + B·C using the Consensus Theorem. Which term is redundant?
B·C is redundant A·B is redundant Ā·C is redundant None are redundant
💡 View Solution Solution & Explanation: B·C is redundant . By Consensus (X=A, Y=B, Z=C), the B·C term is always covered by A·B or Ā·C. Simplified: Y = A·B + Ā·C.
I2: NAND-NAND Gate Count How many 2-input NAND gates implement Y = A·B + C·D in 2-level NAND-NAND form?
3 NAND gates 2 NAND gates 4 NAND gates 6 NAND gates
💡 View Solution Solution & Explanation: 3 NAND gates . NAND1=(A·B)̄, NAND2=(C·D)̄, NAND3=NAND(NAND1,NAND2)=A·B+C·D by De Morgan's.
I3: K-Map All-1s Grouping A 2-variable K-Map (A, B) has all minterms = 1 (m0,m1,m2,m3). What is the simplest result?
Y = 1 Y = A·B Y = A + B Y = A ⊕ B
💡 View Solution Solution & Explanation: Y = 1 . When all minterms = 1, it is a tautology — the function is always 1, regardless of inputs.
C1: CMOS NAND Transistor Count How many transistors does a 2-input static CMOS NAND gate use in total?
4 Transistors (2P + 2N) 2 Transistors 6 Transistors 8 Transistors
💡 View Solution Solution & Explanation: 4 Transistors : 2 PMOS (parallel PUN) + 2 NMOS (series PDN) = 4 total.
C2: PMOS Conduction Condition A PMOS transistor — under what gate voltage does it turn ON?
Gate input = 0 (LOW) Gate input = 1 (HIGH) Always conducting Never conducting
💡 View Solution Solution & Explanation: Gate input = 0 (LOW) . PMOS is active-LOW — it conducts when gate = 0. Opposite of NMOS.
C3: Complementary CMOS Property In static CMOS, what is the relationship between the Pull-Up Network (PUN) and Pull-Down Network (PDN)?
PUN and PDN are dual/complementary networks PUN and PDN are identical networks PUN is active-HIGH, PDN is floating There is no fixed relationship
💡 View Solution Solution & Explanation: PUN and PDN are dual/complementary networks . When PUN is ON (pulling Y to VDD), PDN must be OFF (blocking GND), and vice-versa.
