In a NOR-based SR Latch, what input condition causes an invalid / undefined state (S and R both HIGH)?
SR Latch (NOR): S=1, R=1 โ Q=? , Qฬ=?
Solution & Explanation: S = 1, R = 1 creates an invalid condition in a NOR SR latch because both Q and Qฬ are forced to 0, breaking the complementary output rule.
B2: D Flip-Flop Characteristic Equation
What is the next-state equation Q(next) for a standard D Flip-Flop on the active clock edge?
Q(t+1) = ?
Solution & Explanation: Q(t+1) = D. The D (Data) flip-flop captures the input D on the rising clock edge and transfers it to output Q.
B3: JK Flip-Flop Toggle Condition
In a JK Flip-Flop, what happens to output Q when J = 1 and K = 1 on a clock pulse?
J = 1, K = 1 โ Q(t+1) = ?
Solution & Explanation: Toggles output. J=1, K=1 forces the JK flip-flop to invert its current state on each active clock edge.
I1: Setup Time Definition
What is the definition of Setup Time ($t_{su}$) in flip-flop timing analysis?
Timing Constraint: t_su
Solution & Explanation: Setup time ($t_{su}$) is the minimum time window the data signal must remain valid and stable before the active clock edge arrives.
I2: T Flip-Flop Frequency Divider
Connecting T=1 on a T Flip-Flop driven by clock frequency $f_{clk}$ produces what output frequency at Q?
f_out = f_clk / ?
Solution & Explanation: $f_{clk} / 2$. Since output Q toggles once per clock period, the output square wave period doubles, halving the frequency.
I3: Master-Slave Race Condition
How does a Master-Slave Flip-Flop eliminate transparency race conditions present in simple level-triggered latches?
Master (Clk) + Slave (!Clk)
Solution & Explanation: Master latch samples data when CLK=1 while Slave is isolated. When CLK transitions to 0, Master locks and Slave updates output Q, preventing continuous race-through.
C1: Transmission Gate D-Latch CMOS Count
How many total transistors are required for a standard CMOS Transmission-Gate D-latch (with feedback inverter)?
If static timing analysis reveals a Hold Time violation ($t_{hold} > t_{clk \to q} + t_{comb} - t_{skew}$), how can it be resolved?
Hold Violation: Add delay to data path
Solution & Explanation: Insert delay buffers in the data path. Hold violations are independent of clock period; adding data delay ensures data stays stable long enough after clock edge.
C3: Dynamic CMOS Charge Sharing
In dynamic C2MOS flip-flops, what physical effect can cause soft errors if clock edges have very slow rise/fall times?
Slow Clk Edge โ Charge Redistribution
Solution & Explanation: Charge sharing between dynamic internal capacitance and output load capacitance can corrupt logic levels when both PMOS and NMOS conduct during slow clock transitions.
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